1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, relates to a semiconductor memory device capable of being stably accessed at a high speed with low current consumption. More particularly, the present invention relates to a memory cell structure of a semiconductor memory device such as DRAM (Dynamic Random Access Memory) that requires refresh of the data stored therein.
2. Description of the Background Art
FIG. 44 is a diagram schematically showing the structure of an Pay portion of a conventional DRAM (dynamic Random Access Memory). FIG. 44 exemplarily shows 2-bit memory cells MC1 and MC2, In FIG. 44, the memory cell MC1 is located corresponding to the intersection of a word line WL1 and a bit line BL, and the memory cell MC2 is located corresponding to the intersection of a word line WL2 and a bit line /BL. The memory cell MC1 includes a memory cell capacitor CS1 for storing information, and an access transistor MQ1 for connecting the capacitor CS1 to the bit line BL according to a word line selection signal xcfx86WL1 on the word line WL1. The memory cell MC2 includes a capacitor CS2 for storing information, and an access transistor MQ2 for connecting the capacitor CS2 to the bit line /BL according to a word line selection signal xcfx86WL2 on the word line WL2. These access transistors MQ1 and MQ2 are each formed of an N-channel MOS transistor (insulated-gate field effect transistor).
A sense amplifier SA activated in response to activation of a sense amplifier activation signal xcfx86SA for differentially amplifying and latching voltages on the bit lines BL and /BL is provided on the bit lines BL and /BL.
A cell plate voltage at a predetermined voltage level is applied to respective electrode nodes (cell plate nodes) of the capacitors CS1 and CS2. In the memory cells MC1 and MC2, charges corresponding to the stored data are retained at storage nodes SN1 and SN2. Now, the operation of the DRAM shown in FIG. 44 will be described with reference to a signal waveform diagram shown in FIG. 45.
In the standby state, the word line selection signals xcfx86WL1 and xcfx86WL2 are both held at L level, and in the memory cells MC1 and MC2, the access transistors MQ1 and MQ2 are both in the OFF state. The bit lines BL and /BL are precharged and equalized to an intermediate voltage level by a not-shown bit line precharge/equalize circuit.
When an active cycle is started, a row selection operation is performed according to an external address signal, and a word line corresponding to the addressed row is driven to the selected state. It is now assumed that the word line WL1 is selected and the voltage level of the word line selection signal xcfx86WL1 is raised, as shown in FIG. 45. In this case, in the memory cell MC1, the access transistor MQ1 is turned ON, and charges accumulated in the storage node SN1 of the capacitor CS1 are transmitted onto the bit line BL Since there is no memory cell at the intersection of the bit line /BL and word line WL1, the bit line /BL is kept at the precharge voltage level FIG. 45 shows exemplary signal waveforms in the case where the L-level data is read from the memory cell MC1 onto the bit line BL.
When the voltage difference between the bit lines BL and /BL is sufficiently developed, the sense amplifier activation signal xcfx86SA is activated. Accordingly, the sense amplifier SA differentially amplifies the voltages on the bit lines BL and /BL, so that the voltage levels on the bit lines BL and /BL are respectively driven to the ground voltage level and power supply voltage level and latched.
When the active cycle is completed, the word line selection signal xcfx86WL1 is driven to the non-selected state, whereby the access transistor MQ1 is turned OFF Subsequently, the sense amplifier activation signal xcfx86SA is deactivated, whereby the sense amplifier SA is rendered inactive. The bit lines BL and /BL are restored to the precharge voltage level.
As shown in FIG. 44, the memory cells MC1 and MC2 of the DRAM store information in the respective capacitors CS1 and CS2 in the form of charges. The storage node electrodes SN1 and SN2 of these capacitors are respectively connected to the access transistors MQ1 and MQ2, and therefore the charges stored in the capacitors CS1 and CS2 are discharged to the substrate due to a leak current Moreover, in the case where the voltage levels on the bit lines BL and /BL change according to the selected memory cell data, the charges accumulated in the capacitor of the non-selected memory cell leak through the access transistor. Accordingly, in order to compensate for the change in the charge accumulation amount due to leakage of the charges stored in the storage nodes SN1 and SN2, a refresh operation is performed in the DRAM. In the refresh operation of the memory cell MC1, the data in the memory cell MC1 is read onto the bit line BL, and then amplified by the sense amplifier SA and rewritten to the memory cell MC1. Thus, the stored data in the memory cell MC1 is restored. This refresh operation must be performed periodically.
In order to achieve increase in operation speed of the semiconductor memory device, reduction in current consumption and size of a processing system, and the like, the elements of the semiconductor memory device are reduced in dimensions. As a result of such dimensional reduction of the elements, the memory cell capacitors have a reduced area, and thus have a reduced capacitance value. The memory cell capacitor having a reduced capacitance value has a reduced charge storage amount (Q=Vxc2x7C) even with the data at the same voltage level being written thereto. Therefore, even a slight amount of leak current causes a significant change in the voltage level of the storage data, thereby degrading the data retention characteristics. In order to compensate for such degradation in data retention characteristics, a refresh cycle must be reduced. However, an external processing device cannot access the DRAM during the refresh operation. Therefore, such a reduced refresh cycle results in degradation in performance of the processing system, Moreover, the reduced refresh cycle increases current consumption for the refresh operation. In particular, the condition of low standby current as required in the data retention mode (e.g., sleep mode) of a battery-driven portable equipment or the like cannot be sated. As a result, refreshing with such a reduced refresh cycle cannot be applied to applications such as the battery-driven portable equipment requiring low current consumption.
A pseudo SRAM (PSRAM) for operating the DRAM like an SRAM (Static Random Access Memory) is known as one method to solve the problems regarding the refresh of the DRAM This PSRAM is configured to successively perform, within a single memory access cycle, the two cycles of a normal data write/read cycle and a refresh cycle. Thus, the refresh can be performed in a single access cycle and can be concealed from the external access, thereby enabling the DRAM to be apparently operated as SRAM.
However, the PSRAM is requited to perform the operation of two cycles within a single access cycle, and therefore the cycle time cannot be reduced. In particular, it is difficult for the PSRAM to realize the operation cycle of 70 to 80 nanoseconds (ns) required for the SRAM in the current 0.18-micron manufacturing technology.
The structure in which a refresh port and a normal access port are separately provided so as to internally perform the refresh operation of the DRAM independently of the external access by using the refresh port is shown in, e.g., Japanese Patent Laid-Open Applications Nos. 2-21488, 61-11993 and 55-153194.
However, in these conventional examples, in the case where the memory tells are reduced in data retention characteristics due to the dimensional reduction thereof, the internal refresh interval must be reduced Therefore, current consumption in the data retention mode such as sleep mode cannot be reduced.
Moreover, the problems resulting from the dimensional reduction of the elements also cause a degraded sense margin of the sense amplifier. More specifically, if the capacitance value of the memory cell capacitors is reduced, a read voltage read onto the bit line BL or /BL is reduces. This read voltage is normally determined by the ratio of the capacitance value Cs of the memory cell capacitor to the capacitance value Cb of the bit line. Accordingly, such a reduced capacitance value of the memory cell capacitor results in a reduced read voltage. The sense amplifier SA, which amplifies the read voltage, cannot accurately perform the sensing operation if the read voltage is reduced, resulting in a degraded sense margin. Such degradation in sense margin due to the dimensional reduction of the elements is not at all considered in the above-mentioned conventional examples.
Moreover, the bit lines BL and /BL are in an electrically floating state in selection of a word line. In the case where the selected word line is capacitively coupled to the bit line through the gate capacitance of the access transistor, the voltage level on the bit line having the memory cell connected thereto is raised, and the voltage level (read voltage) of the data read from the memory cell is changed. On the other hand, since the other reference bit line does not have any memory cell connected thereto, such capacitive coupling through the access transistor is not caused. With the elements being reduced in dimensions and the read voltage being reduced, even a slight voltage change due to the capacitive coupling through the gate capacitance greatly affects the read voltage, whereby the memory cell data cannot be sensed accurately.
It is an object of the present invention to provide a semiconductor memory device having an excellent data retention characteristics.
It is another object of the present invention to provide a semiconductor memory device capable of stably reading the memory cell data.
It is still another object of the present invention to provide a semiconductor memory device capable of reducing current consumption in the standby state.
It is yet another object of the present invention to provide a semiconductor memory device capable of implementing a high-speed data processing system.
It is further another object of the present invention to provide a semiconductor memory device suitable for use in applications such as battery-driven portable equipment.
A semiconductor memory device according to the present invention includes: a plurality of memory cells arranged in rows and columns; a plurality of normal bit line pairs provided corresponding to the respective memory cell columns and each having the memory cells of a corresponding column connected thereto; and a plurality of refresh bit line pairs provided corresponding to the respective memory cell columns and each having the memory cells of a corresponding column connected thereto. Each normal bit line pair has first and second normal bit lines, and each refresh bit line pair has first and second refresh bit lines.
Each memory cell includes a first transistor provided between the first normal bit line of a corresponding column and a first storage node, a first capacitance provided between the first storage node and a constant voltage source, a second transistor provided between the first refresh bit line of the corresponding column and the first storage node, a third transistor provided between the second normal bit line of the corresponding column and a second storage node, a second capacitance provided between the second storage node and the constant voltage source, and a fourth transistor provided between the second storage node and the second refresh bit line of the corresponding column.
The semiconductor memory device of the present invention further includes: a plurality of normal word lines provided corresponding to the respective memory cell rows and each having the first and third transistors of the memory cells of a corresponding row connected thereto; and a plurality of refresh word lines provided corresponding to the respective memory cell rows and each having the second and fourth transistors of the memory cells of a corresponding row connected thereto.
When a memory cell is selected, the memory cell capacitances are connected to the respective bit lines of a corresponding bit line pair Thus, complementary data is read onto the bit line pair, whereby the read voltage can be effectively increased Accordingly, even if the elements have been dimensionally reduced, a sufficiently large read voltage can be produced, whereby the sensing operation can be stably performed.
Moreover, the refresh bit lines and normal bit lines are separately provided. Therefore, the refresh operation can be performed independently of an external access As a result, the refresh operation can be effectively concealed from an outside, whereby high-speed external access can be realized.
Moreover, by reading the complementary data onto the bit line pair, the refresh cycle can be increased to such an extent that the voltage difference between the bit lines corresponds to substantially the same bit line read voltage as that of the conventional examples. Accordingly, the refresh interval can be increased, As a result, fast access with a reduced refresh current and a reduced waiting time of a processor can be realized.
Moreover, the read voltage is effectively increased as compared to the conventional examples. Therefore, the sensing operation can be started at a faster timing, whereby high-speed access can be realized.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.